1. Field of the Invention
This invention relates to a semiconductor device having a multi-chip stack structure, where a solid state device and one or more semiconductor chips are stacked and joined, and a manufacturing method for the same, as well as a semiconductor chip which is used in such a manufacturing method.
2. Description of Related Art
A semiconductor device having a multi-chip stack structure where one or more semiconductor chips are stacked on the surface of a solid state device such as a semiconductor chip or a wiring substrate has been conventionally known.
FIG. 30(a) and FIG. 30(b) are illustrative cross sectional diagrams showing the structure of a conventional semiconductor device having a multi-chip stack structure. A semiconductor device having such a structure is disclosed in, for example, “Proceedings of the 2003 VMIC (VLSI Multi-Level Interconnection) Conference,” M. Hoshino et al., September 2003, pp. 243-246.
This semiconductor device 101 includes a solid state device 102, such as a wiring substrate or a semiconductor chip, and a plurality of (2, in this example) semiconductor chips 103 which are stacked on solid state device 102. FIG. 30(a) shows an arrangement of solid state device 102 and two semiconductor chips 103, and FIG. 30(b) shows a portion where two semiconductor chips 103 are joined and the area in the vicinity thereof in an enlarged view.
These semiconductor chips 103 have structures which are similar to each other, and a functional element 104 (not shown in FIG. 30(a)) is formed on one of the surfaces (hereinafter referred to as “front surface”) 103a of each chip. Each semiconductor chip 103 is joined to solid state device 102 in a manner where its front surface 103a faces the solid state device 102 side in a so-called face-down style.
Each semiconductor chip 103 is provided with a semiconductor substrate 108, where through holes 105 are formed so as to penetrate semiconductor substrate 108 in the direction of its thickness. Inside of each through hole 105 is almost completely filled with a feedthrough electrode 107. Feedthrough electrode 107 is electrically connected to functional element 104 so that feedthrough electrode 107 allows an electrical connection between surface (hereinafter referred to as “rear surface”) 103b on the side opposite front surface 103a of semiconductor chip 103 and functional element 104.
An insulating film 106 (not shown in FIG. 30(a)) is formed on the inner wall of through hole 105 so that insulating film 106 electrically insulates feedthrough electrode 107 from semiconductor substrate 108.
The surfaces of semiconductor substrate 108 on the front surface 103a side and on the rear surface 103b side are respectively covered with a front surface protective film 109 and a rear surface protective film 110. Openings 109a and 110a are respectively formed in front surface protective film 109 and in rear surface protective film 110.
On the front surface 103a side, feedthrough electrode 107 has a surface which is approximately on the same plane as the surface of semiconductor substrate 108, and the surface of this feedthrough electrode 107 is exposed from opening 109a of front surface protective film 109. Meanwhile, on the rear surface 103b side, feedthrough electrode 107 penetrates through opening 110a of rear surface protective film 110, and has an exposed surface which is approximately on the same plane as rear surface 103b (surface of rear surface protective film 110). Rear surface 103b of semiconductor chip 103 is slightly elevated in the vicinity of feedthrough electrode 107.
A front surface side connection member 111 and a rear surface side connection member 112 are respectively connected to exposed portions of feedthrough electrode 107 on the front surface 103a side and on the rear surface 103b side. Front surface side connection member 111 is in the form of a bump that protrudes from front surface 103a, while rear surface side connection member 112 is in film form and covers the end surface (surface exposed from rear surface protective film 110) on the rear surface 103b side of feedthrough electrode 107. Rear surface side connection member 112 slightly protrudes from rear surface 103b. 
Front surface side connection member 111 of one semiconductor chip 103 and rear surface side connection member 112 of another semiconductor chip 103 are joined between two adjacent semiconductor chips 103.
In reference to FIG. 30(a), a solid state device side connection member 113 in film form for electrical connection and mechanical attachment to a semiconductor chip 103 is formed on the surface of solid state device 102 on the side on which semiconductor chip 103 is connected. Solid state device side connection member 113 and front surface side connection member 111 of an adjacent semiconductor chip 103 are joined.
In the above-described structure, functional elements 104 of any semiconductor chip 103 are electrically connected to solid state device 102.
FIG. 31(a) and FIG. 31(b) are illustrative cross sectional diagrams showing a manufacturing method for a semiconductor device 101. Such a manufacturing method is disclosed in, for example, “Proceedings of the 2003 Electronic Compounds and Technology Conference,” Kazumasa Tanida et al., May 2003, pp. 1084-1089.
Semiconductor chips 103 are held one at a time by suction, and are stacked on solid state device 102 by means of a bonding tool 122 which can hold a semiconductor chip 103 by suction. First, solid state device 102 is mounted on a bonding stage 121 in a state where the surface on which solid state device side connection member 113 has been formed faces upward and is approximately horizontal. In addition, a first semiconductor chip 103 is held by bonding tool 122 which attracts the rear surface 103b of the chip in a state where the front surface 103a of the chip faces downward and is approximately horizontal. The surface of bonding tool 122 which makes contact with semiconductor chip 103 is approximately flat.
Subsequently, bonding tool 122 is moved so that the surface of solid state device 102 on which solid state device side connection member 113 has been formed and front surface 103a of semiconductor chip 103 face each other, and then, solid state device side connection member 113 and front surface side connection member 111 are positioned. Then, in this state, bonding tool 122 is lowered, and thereby, front surface side connection member 111 is pressed against solid state device side connection member 113 with an appropriate load. As a result of this, solid state device side connection member 113 and front surface side connection member 111 are joined.
Bonding tool 122 may be able to generate an ultrasonic vibration. In this case, bonding tool 122 applies an ultrasonic vibration to the portion where solid state device side connection member 113 and front surface side connection member 111 make contact with each other (are joined), if necessary. When joining of solid state device side connection member 113 to front surface side connection member 111 is completed, bonding tool 122 releases semiconductor chip 103 which was held by suction.
Next, bonding tool 122 holds a second semiconductor chip 103 by suction, in the same manner as in the case of first semiconductor chip 103.
Subsequently, bonding tool 122 is moved so that rear surface 103b of the semiconductor chip 103 that has been placed on and joined to solid state device 102 and front surface 103a of the semiconductor chip 103 which is held by bonding tool 122 face each other, and then, rear surface side connection member 112 and front surface side connection member 111 are positioned.
In this state, bonding tool 122 is lowered, and thereby, this rear surface side connection member 112 and this front surface side connection member 111 are joined (see FIG. 31(a)). At this time, bonding tool 122 applies an ultrasonic vibration to the joining portion, if necessary. When joining of rear surface side connection member 112 to front surface side connection member 111 is completed, bonding tool 122 releases semiconductor chip 103 which was held by suction.
As a result of this, electrical connections and mechanical attachments are achieved between solid state device 102 and semiconductor chip 103, as well as between a plurality of semiconductor chips 103.
However, rear surface side connection member 112 is provided on rear surface 103b of semiconductor chip 103 on which bonding tool 122 makes contact, so as to protrude from rear surface 103b (surface of rear surface protective film 110). Therefore, rear surface side connection member 112 is pressed against bonding tool 122 so as to be deformed in a manner where it spreads to the sides (in directions along rear surface 103b) when semiconductor chip 103 is pressed against solid state device 102 or another semiconductor chip 103 in a state where its rear surface 103b is held by bonding tool 122 (see FIG. 31(b)). As a result of this, there is a risk that two rear surface side connection members 112 may be electrically short-circuited, causing a short-circuiting defect in the case where these rear surface side connection members 112 are placed in proximity.
In the same manner, front surface side connection member 111 also protrudes from front surface 103a (surface of front surface protective film 109), and therefore, front surface side connection member 111 is deformed in a manner where it spreads to the sides, together with rear surface side connection member 112, when pressed against rear surface side connection member 112 at the time when two semiconductor chips 103 are joined. There is a risk that short-circuiting defects will be caused by such deformations.
In addition, an ultrasonic vibration is provided by, for example, bonding tool 122 when semiconductor chip 103 is held by bonding tool 122 by suction, and thereby, in some cases, semiconductor chip 103 may be shifted relative to bonding tool 122 in a direction along the contact surface therebetween. That is, friction may be caused between semiconductor chip 103 and bonding tool 122.
As a result of this, cracks 114 and 115 may be caused in rear surface protective film 110 and insulating film 106, respectively (see FIG. 31(b)). In some cases, a crack may be caused in semiconductor substrate 108. In the following, these cracks are generally referred to as “chip cracks.”
In addition, in the case where semiconductor substrate 108 is made of silicon, microscopic chips of silicon (hereinafter referred to as “silicon dust”) that have been generated during the manufacturing process of semiconductor chip 103 or semiconductor device 101 may stick to bonding tool 122 or rear surface 103b of semiconductor chip 103. In such a case, semiconductor chip 103 is pressed by bonding tool 122 in a state where silicon dust intervenes between bonding tool 122 and rear surface 103b of semiconductor chip 103, and thereby, a chip crack (specifically, crack 114 in rear surface protective film 110) is generated.
Furthermore, in the case where an ultrasonic vibration is provided by bonding tool 122, rear surface side connection member 112 that makes contact with bonding tool 122 is deformed by this ultrasonic vibration. The ultrasonic vibration that is to be conveyed to portions where front surface side connection member 111 makes contact with solid state device side connection member 113 and rear surface side connection member 112 of another semiconductor chip 103 is attenuated due to the deformation of rear surface side connection member 112 which makes contact with bonding tool 122. As a result of this, there is a risk that joining of semiconductor chip 103 to solid state device 102 or another semiconductor chip 103 may not be sufficiently achieved.
Furthermore, at the time of joining, rear surface side connection member 112 that has been formed on rear surface 103b makes contact with bonding tool 122, and thereby, the surface of rear surface side connection member 112 is contaminated, and thus, there is a risk that the joining (connection) defect may be caused in the case where an additional semiconductor chip 103 or the like is joined to this rear surface side connection member 112.